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FEATURES High Speed (1.65 s) 12-Bit ADC Four Simultaneously Sampled Inputs Four Track/Hold Amplifiers 0.35 s Track/Hold Acquisition Time 1.65 s Conversion Time per Channel HW/SW Select of Channel Sequence for Conversion Single Supply Operation Selection of Input Ranges: 10 V, 5 V for AD7864-1 2.5 V for AD7864-3 0 V to 2.5 V, 0 V to 5 V for AD7864-2 High Speed Parallel Interface Which Also Allows Interfacing to 3 V Processors Low Power, 90 mW Typ Power Saving Mode, 20 W Typ Overvoltage Protection on Analog Inputs APPLICATIONS AC Motor Control Uninterrupted Power Supplies Data Acquisition Systems Communications
4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC AD7864
FUNCTIONAL BLOCK DIAGRAM
AVDD STBY VIN1A VIN1B VIN2A VIN2B VIN3A VIN3B VIN4A VIN4B FRSTDATA BUSY EOC
CONVERSION CONTROL LOGIC TRACK/HOLD 4 SIGNAL SCALING SIGNAL SCALING MUX SIGNAL SCALING SIGNAL SCALING SOFTWARE LATCH DB0-DB3 12-BIT ADC OUTPUT DATA REGISTERS
VREF
6k
VREF GND
DVDD VDRIVE
2.5V REFERENCE
DGND AGND RD DB11 DB0 CS WR
AD7864
INT/EXT CLOCK SELECT
INT CLOCK
CONVST SL1 SL2 SL3 SL4 H/S SEL
CLKIN INT/EXT AGND AGND CLK
GENERAL DESCRIPTION
maximum throughput is 130 kSPS for the read during conversion sequence operation. The throughput rate for the read after conversion sequence operation will depend on the read cycle time of the processor. See Timing and Control section. The AD7864 is available in a small (0.3 sq. inch area) 44-lead MQFP.
PRODUCT HIGHLIGHTS
The AD7864 is a high speed, low power, 4-channel simultaneous sampling 12-bit A/D converter that operates from a single +5 V supply. The part contains a 1.65 s successive approximation ADC, four track/hold amplifiers, 2.5 V reference, on-chip clock oscillator, signal conditioning circuitry and a high speed parallel interface. The input signals on four channels are sampled simultaneously, thus preserving the relative phase information of the signals on the four analog inputs. The part accepts analog input ranges of 10 V, 5 V (AD7864-1), 0 V to 2.5 V, 0 V to 5 V for AD7864-2 and 2.5 V (AD7864-3). The part allows any subset of the four channels to be converted in order to maximize the throughput rate on the selected sequence. The channels to be converted can be selected via either hardware (channel select input pins) or software (programming the channel select register). A single conversion start signal (CONVST) simultaneously places all the track/holds into hold and initiates conversion sequence for the selected channels. The EOC signal indicates the end of each individual conversion in the selected conversion sequence. The BUSY signal indicates the end of the conversion sequence. Data is read from the part by means of a 12-bit parallel data bus using the standard CS and RD signals. Maximum throughput for a single channel is 500 kSPS. For all four channels the REV. A
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1. The AD7864 features four Track/Hold amplifiers and a fast (1.65 s) ADC allowing simultaneous sampling and then conversion of any subset of the four channels. 2. The AD7864 operates from a single +5 V supply and consumes only 90 mW typ making it ideal for low power and portable applications. Also see Standby Mode Operation. 3. The part offers a high speed parallel interface for easy connection to microprocessors, microcontrollers and digital signal processors. 4. The part is offered in three versions with different analog input ranges. The AD7864-1 offers the standard industrial input ranges of 10 V and 5 V; the AD7864-3 offers the common signal processing input range of 2.5 V; the AD7864-2 can be used in unipolar 0 V to 2.5 V, 0 V to 5 V applications. 5. The part features very tight aperture delay matching between the four input sample-and-hold amplifiers.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD7864-SPECIFICATIONS cations T
Parameter SAMPLE AND HOLD -3 dB Full Power Bandwidth Aperture Delay Aperture Jitter Aperture Delay Matching DYNAMIC PERFORMANCE2 Signal to (Noise + Distortion) Ratio3 @ +25C TMIN to TMAX Total Harmonic Distortion3 Peak Harmonic or Spurious Noise3 Intermodulation Distortion3 2nd Order Terms 3rd Order Terms Channel-to-Channel Isolation3 DC ACCURACY Resolution Relative Accuracy3 Differential Nonlinearity3 AD7864-1 Positive Gain Error3 Positive Gain Error Match3 Negative Gain Error3 Negative Gain Error Match3 Bipolar Zero Error Bipolar Zero Error Match AD7864-3 Positive Gain Error3 Positive Gain Error Match3 Negative Gain Error3 Negative Gain Error Match3 Bipolar Zero Error Bipolar Zero Error Match AD7864-2 Positive Gain Error3 Positive Gain Error Match3 Unipolar Offset Error Unipolar Offset Error Match ANALOG INPUTS AD7864-1 Input Voltage Range Input Resistance AD7864-3 Input Voltage Range Input Resistance AD7864-2 Input Voltage Range Input Current (0 V-2.5 V Option) Input Resistance (0 V-5 V Option) REFERENCE INPUT/OUTPUT VREF IN Input Voltage Range VREF IN Input Capacitance4 VREF OUT Output Voltage VREF OUT Error @ +25C VREF OUT Error TMIN to TMAX VREF OUT Temperature Coefficient VREF OUT Output Impedance A Version1 3 20 50 4
(VDD = +5 V
MIN
5%, AGND = DGND = 0 V, VREF = Internal. Clock = Internal; all specifito TMAX unless otherwise noted.)
B Version 3 20 50 4 Units MHz typ ns max ps typ ns max fIN = 100.0 kHz, fS = 500 kSPS Test Conditions/Comments
70 70 -80 -80 -80 -80 -80 12 1 0.9 3 3 3 3 4 2 3 2 3 2 3 2 3 3 3 2
72 70 -80 -80 -80 -80 -80 12 1/2 0.9 3 3 3 3 3 2
dB min dB min dB max dB max fa = 49 kHz, fb = 50 kHz dB typ dB typ dB max Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max
fIN = 50 kHz Sine Wave Any Channel
No Missing Codes
5, 10 9, 18 2.5 4.5 +2.5, +5 100 9 2.375/2.625 10 2.5 10 20 25 6
5, 10 9, 18 2.5 4.5 +2.5, +5 100 9 2.375/2.625 10 2.5 10 20 25 6
Volts k min Volts k min Volts nA max k min VMIN/VMAX pF max V nom mV max mV max ppm/C typ k typ 2.5 V 5%
See Reference Section
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REV. A
AD7864
Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL DB11-DB0 High Impedance Leakage Current Capacitance4 Output Coding AD7864-1, AD7864-3 AD7864-2 CONVERSION RATE Conversion Time Track/Hold Acquisition Time2, 3 Throughput Time POWER REQUIREMENTS VDD IDD Normal Mode Standby Mode Power Dissipation Normal Mode Standby Mode A Version 2.4 0.8 10 10 4.0 0.4 10 10
1
B Version 2.4 0.8 10 10 4.0 0.4 10 10
Units V min V max A max pF max V min V max A max pF max
Test Conditions/Comments VDD = 5 V 5% VDD = 5 V 5%
ISOURCE = 400 A ISINK = 1.6 mA
Twos Complement Straight (Natural) Binary 1.65 0.35 130 +5 24 20 120 100 1.65 0.35 130 +5 24 20 120 100 s max s max kSPS max V nom mA max A max mW max W max For One Channel For All Four Channels 5% for Specified Performance (5 A typ) Logic Inputs = 0 V or VDD Typically 4 A Typically 90 mW Typically 20 W
NOTES 1 Temperature ranges are as follows: A, B Versions: -40C to +85C. Note: The A Version is fully specified up to +105C with degraded INL and DNL specifications of 2 LSBs max. 2 Performance measured through full channel (SHA and ADC). 3 See Terminology. 4 Sample tested @ +25C to ensure compliance. Specifications subject to change without notice.
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AD7864 TIMING CHARACTERISTICS1, 2
Parameter tCONV tACQ tBUSY tWAKE-UP--External VREF tWAKE-UP--Internal VREF3 t1 t2 Read Operation t3 t4 t5 t6 4 t7 5 t8 t9 t10 t11 t12 Write Operation t13 t14 t15 t16 t17
(VD = +5 V 5%, AGND = DGND = 0 V, V REF = Internal, Clock = Internal; all specifications TMIN to TMAX unless otherwise noted.)
Units s max Clock Cycles s max s max s max s max ms max ns min ns min ns min ns min ns min ns max ns max ns min ns max ns min ns min ns max ns max ns max ns min ns min ns min ns min ns min ns min Test Conditions/Comments Conversion Time, Internal Clock Conversion Time, External Clock CLKIN = 5 MHz Acquisition Time Selected Number of Channels Multiplied by (tCONV + EOC Pulsewidth)--EOC Pulsewidth STBY Rising Edge to CONVST Rising Edge STBY Rising Edge to CONVST Rising Edge CONVST Pulsewidth CONVST Rising Edge to BUSY Rising Edge CS to RD Setup Time CS to RD Hold Time Read Pulsewidth Data Access Time After Falling Edge of RD, VDRIVE = 5 V Data Access Time After Falling Edge of RD, VDRIVE = 3 V Bus Relinquish Time After Rising Edge of RD Time Between Consecutive Reads EOC Pulsewidth RD Rising Edge to FRSTDATA Edge (Rising or Falling) EOC Falling Edge to FRSTDATA Falling Delay EOC to RD Delay WR Pulsewidth CS to WR Setup Time WR to CS Hold Time Input Data Setup Time of Rising Edge of WR Input Data Hold Time
A, B Versions 1.65 13 2.6 0.34 No. of Channels x (tCONV + t9) - t9 2 6 35 70 0 0 35 35 40 5 30 10 75 180 70 15 0 20 0 0 5 5
NOTES 1 Sample tested at +25C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V. 2 See Figures 7, 8 and 9. 3 Refer to the Standby Mode Operation section. The MAX specification of 6 ms is valid when using a 0.1 F decoupling capacitor on the V REF pin. 4 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V. 5 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice.
1.6mA
TO OUTPUT 50pF
1.6V
400 A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
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REV. A
AD7864
ABSOLUTE MAXIMUM RATINGS*
(TA = +25C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Analog Input Voltage to AGND AD7864-1 ( 10 V Input Range) . . . . . . . . . . . . . . . . 20 V AD7864-1 ( 5 V Input Range) . . . . . . . . . . . -7 V to +20 V AD7864-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . -7 V to +20 V AD7864-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . -1 V to +20 V Reference Input Voltage to AGND . . . -0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . -0.3 V to VDD + 0.3 V Digital Output Voltage to DGND . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Commercial (A, B Version) . . . . . . . . . . . . -40C to +85C
Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150C MQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD7864AS-1 AD7864BS-1 AD7864AS-3 AD7864AS-2
Input Ranges 5 V, 10 V 5 V, 10 V 2.5 V 0 V to 2.5 V, 0 V to 5 V
Relative Accuracy 1 LSB 0.5 LSB 1 LSB 1 LSB
Temperature Range* -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description Plastic Lead Quad Flatpack Plastic Lead Quad Flatpack Plastic Lead Quad Flatpack Plastic Lead Quad Flatpack
Package Option S-44 S-44 S-44 S-44
*The A Version is fully specified up to +105C with degraded INL and DNL specifications of 2 LSBs max.
PIN CONFIGURATION
DGND VDRIVE
DVDD
EOC
DB0
DB2
DB1
DB3
DB4
44 43 42 41 40 39 38 37 36 35 34 BUSY 1 FRSTDATA 2 CONVST 3 CS 4 RD 5 WR 6 SL1 7 SL2 8 SL3 9 SL4 10 H/S SEL 11 12 13 14 15 16 17 18 19 20 21 22 AGND AGND VIN3B VIN4A VIN4B VIN2B VIN2A VIN1B VIN1A STBY VIN3A
PIN 1 IDENTIFIER
DB5
DB6 33 DB7 32 DB8 31 DB9 30 DB10 29 DB11 28 CLKIN 27 INT/EXT CLK 26 AGND 25 AVDD 24 VREF 23 VREFGND
AD7864
TOP VIEW (Not to Scale)
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7864 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
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AD7864
PIN FUNCTION DESCRIPTION Pin 1 2 3 Mnemonic BUSY FRSTDATA CONVST Description Busy Output. The busy output is triggered high by the rising edge of CONVST and remains high until conversion is completed on all selected channels. First Data Output. FRSTDATA is a logic output which, when high, indicates that the Output Data Register Pointer is addressing Register 1--See Accessing the Output Data Registers. Convert Start Input. Logic Input. A low-to-high transition on this input puts all track/holds into their hold mode and starts conversion on the selected channels. In addition, the state of the Channel Sequence Selection is also latched on the rising edge of CONVST. Chip Select Input. Active Low Logic Input. The device is selected when this input is active. Read Input. Active Low Logic Input that is used in conjunction with CS low to enable the data outputs. Ensure the WR pin is at logic high while performing a read operation. Write Input. A rising edge on the WR input, with CS low and RD high, latches the logic state on DB0 to DB3 into the channel select register. Hardware Channel Select. Conversion sequence selection can also be made via the SL1-SL4 pins if H/S SEL is logic zero. The selection is latched on the rising edge of CONVST. See Selecting a Conversion Sequence. Hardware/Software Select Input. When this pin is at a Logic 0, the AD7864 conversion sequence selection is controlled via the SL1-SL4 input pins. When this pin is at Logic 1, the sequence is controlled via the channel select register. See Selecting a Conversion Sequence. Analog Ground. General Analog Ground. This AGND pin should be connected to the system's AGND plane. Analog Inputs. See Analog Input section. Analog Ground. Analog Ground reference for the attenuator circuitry. This AGND pin should be connected to the system's AGND plane. Analog Inputs. See Analog Input section. Standby Mode Input. TTL-compatible input that is used to put the device into the power save or standby mode. The STBY input is high for normal operation and low for standby operation. Reference Ground. Ground reference for the part's on-chip reference buffer. The V REF GND pin should be connected to the system's AGND plane. Reference Input/Output. This pin provides access to the internal reference (2.5 V 5%) and also allows the internal reference to be overdriven by an external reference source (2.5 V). A 0.1 F decoupling capacitor should be connected between this pin and AGND. Analog Positive Supply Voltage, +5.0 V 5%. Analog Ground. Analog Ground reference for the DAC circuitry. Internal/External Clock Select Input. When this pin is at a Logic 0, the AD7864 uses its internally generated master clock. When this pin is at Logic 1, the master clock is generated externally to the device. Conversion Clock Input. This is an externally applied clock that allows the user to control the conversion rate of the AD7864. Each conversion needs fourteen clock cycles in order for the conversion to be completed and an EOC pulse to be generated. The clock should have a duty cycle that is no worse than 60/40. See Using an External Clock. Data Bit 11 is the MSB, followed by Data Bit 10 to Data Bit 6. Three-state TTL outputs. Output coding is 2s complement for the AD7864-1 and AD7864-3. Output coding is straight (natural) binary for the AD7864-2. Positive supply voltage for digital section, +5.0 V 5%. A 0.1 F decoupling capacitor should be connected between this pin and AGND. Both DVDD and AVDD should be externally tied together. This pin provides the positive supply voltage for the output drivers (DB0 to DB11), BUSY, EOC and FRSTDATA. It is normally tied to DV DD. VDRIVE should be decoupled with a 0.1 F capacitor. It allows improved performance when reading during the conversion sequence. To facilitate interfacing to 3 V processors and DSPs the output data drivers may also be powered by a 3 V 10% supply . Digital Ground. Ground reference for digital circuitry. This DGND pin should be connected to the system's AGND plane at the AGND pin. Data Bit 5 to Data Bit 4. Three-state TTL Outputs. Data Bit 3 to Data Bit 0. Bidirectional Data Pins. When a read operation takes place, these pins are threestate TTL outputs. The channel select register is programmed with the data on the DB0-DB3 pins with standard CS and WR signals. DB0 represents Channel 1 and DB3 which represents Channel 4. End-of-Conversion. Active low logic output indicating conversion status. The end of each conversion in a conversion sequence is indicated by a low-going pulse on this line.
4 5 6 7-10
CS RD WR SL1-SL4
11
H/S SEL
12 13-16 17 18-21 22 23 24
AGND VIN4X, VIN3X AGND VIN2X, VIN1X STBY VREF GND VREF
25 26 27
AVDD AGND INT/EXT CLK
28
CLKIN
29-34
DB11-DB6
35 36
DVDD VDRIVE
37 38, 39 40-43
DGND DB5, DB4 DB3-DB0
44
EOC
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REV. A
AD7864
TERMINOLOGY
Signal to (Noise + Distortion) Ratio Channel-to-Channel Isolation
This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Channel-to-Channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale 50 kHz sine wave signal to all nonselected input channels and determining how much that signal is attenuated in the selected channel. The figure given is the worst case across all four channels.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function.
Differential Nonlinearity
Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7864 it is defined as: THD dB = 20 log
This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Positive Full-Scale Error
()
V22 +V32 +V42 +V52 +V62 V1
where V1 is the rms amplitude of the fundamental and V2, V3, V4 and V5 are the rms amplitudes of the second through the fifth harmonics.
Peak Harmonic or Spurious Noise
This is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal 4 x VREF - 3/2 LSB (AD7864-1 10 V), 2 x VREF - 3/2 LSB (AD7864-1 5 V range) or VREF - 3/2 LSB (AD7864-3, 2.5 V range), after the Bipolar Offset Error has been adjusted out.
Positive Full-Scale Error (AD7864-2, 0 V to 2.5 V and 0 V to 5 V)
Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak.
Intermodulation Distortion
This is the deviation of the last code transition (11 . . . 110 to 11 . . . 111) from the ideal 2 x VREF - 3/2 LSB (AD7864-2 0 V to 5 V range), or VREF - 3/2 LSB (AD7864-2 0 V to 2.5 V range), after the Unipolar Offset Error has been adjusted out.
Bipolar Zero Error (AD7864-1, 10/ 5 V, AD7864-3 , 2.5 V)
This is the deviation of the midscale transition (all 0s to all 1s) from the ideal AGND - 1/2 LSB.
Unipolar Offset Error (AD7864-2, 0 V to 2.5 V and 0 V to 5 V)
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa - fb), while the third order terms include (2 fa + fb), (2 fa - fb), (fa + 2 fb) and (fa - 2 fb). The AD7864 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs.
This is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal AGND + 1/2 LSB.
Negative Full-Scale Error (AD7864-1, 2.5 V) 10/ 5 V, AD7864-3,
This is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal -4 x VREF + 1/2 LSB (AD7864-1 10 V), -2 x VREF + 1/2 LSB (AD7864-1 5 V range) or -VREF + 1/2 LSB (AD7864-3, 2.5 V range), after Bipolar Zero Error has been adjusted out.
Track/Hold Acquisition Time
Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 LSB, after the end of conversion (the point at which the track/hold returns to track mode). It also applies to situations where there is a step input change on the input voltage applied to the selected VINXA/VINXB input of the AD7864. It means that the user must wait for the duration of the track/hold acquisition time after the end of conversion or after a step input change to VINXA/VINXB before starting another conversion, to ensure that the part operates to specification.
REV. A
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AD7864
CONVERTER DETAILS Track/Hold Section
The AD7864 is a high speed, low power, 4-channel simultaneous sampling 12-bit A/D converter that operates from a single +5 V supply. The part contains a 1.65 s successive approximation ADC, four track/hold amplifiers, an internal +2.5 V reference and a high speed parallel interface. There are four analog inputs that can be simultaneously sampled thus preserving the relative phase information of the signals on all four analog inputs. Thereafter, conversions will be completed on the selected subset of the four channels. The part accepts an analog input range of 10 V or 5 V (AD7864-1), 2.5 V (AD7864-3) and 0 V-2.5 V or 0 V-5 V (AD7864-2). Overvoltage protection on the analog inputs of the part allows the input voltage to go to 20 V, (AD7864-1 10 V range), -7 V or +20 V (AD7864-1 5 V range) -1 V to +20 V (AD7864-2) and -7 V to +20 V (AD7864-3) without causing damage or effecting a conversion in progress. The AD7864 has two operating modes Reading Between Conversions and Reading after the Conversion Sequence. These modes are discussed in more detail in the Timing and Control section. A conversion is initiated on the AD7864 by pulsing the CONVST input. On the rising edge of CONVST, all four on-chip track/ holds are placed into hold simultaneously and the conversion sequence is started on all the selected channels. Channel selection is made via the SL1-SL4 pins if H/S SEL is logic zero or via the channel select register if H/S SEL is logic one--see Selecting a Conversion Sequence. The channel select register is programmed via the bidirectional data lines DB0-DB3 and a standard write operation. The selected conversion sequence is latched on the rising edge of CONVST so changing a selection will only take effect once a new conversion sequence is initiated. The BUSY output signal is triggered high on the rising edge of CONVST and will remain high for the duration of the conversion sequence. The conversion clock for the part is generated internally using a laser-trimmed clock oscillator circuit. There is also the option of using an external clock, by tying the INT/ EXT CLK pin logic high, and applying an external clock to the CLKIN pin. However, the optimum throughput is obtained by using the internally generated clock--see Using an External Clock. The EOC signal indicates the end of each conversion in the conversion sequence. The BUSY signal indicates the end of the full conversion sequence and at this time all four Track and Holds return to tracking mode. The conversion results can either be read at the end of the full conversion sequence (indicated by BUSY going low) or as each result becomes available (indicated by EOC going low). Data is read from the part via a 12-bit parallel data bus with standard CS and RD signals--see Timing and Control. Conversion time for each channel of the AD7864 is 1.65 s and the track/hold acquisition time is 0.35 s. To obtain optimum performance from the part, the read operation should not occur during a channel conversion or during the 100 ns prior to the next CONVST rising edge. This allows the part to operate at throughput rates up to 130 kHz for all four channels and achieve data sheet specifications.
The track/hold amplifiers on the AD7864 allows the ADCs to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. The input bandwidth of the track/hold is greater than the Nyquist rate of the ADC even when the ADC is operated at its maximum throughput rate of 500 kSPS (i.e., the track/hold can handle input frequencies in excess of 250 kHz). The track/hold amplifiers acquire input signals to 12-bit accuracy in less than 350 ns. The operation of the track/holds are essentially transparent to the user. The four track/hold amplifiers sample their respective input channels simultaneously, on the rising edge of CONVST. The aperture time for the track/ holds (i.e., the delay time between the external CONVST signal and the track/hold actually going into hold) is typically 15 ns and, more importantly, is well matched across the four track/ holds on one device and also well matched from device to device. This allows the relative phase information between different input channels to be accurately preserved. It also allows multiple AD7864s to sample more than four channels simultaneously. At the end of a conversion sequence, the part returns to its tracking mode. The acquisition time of the track/hold amplifiers begin at this point.
Reference Section
The AD7864 contains a single reference pin, labelled VREF, which either provides access to the part's own +2.5 V reference or to which an external +2.5 V reference can be connected to provide the reference source for the part. The part is specified with a +2.5 V reference voltage. Errors in the reference source will result in gain errors in the AD7864's transfer function and will add to the specified full-scale errors on the part. On the AD7864-1 and AD7864-3, it will also result in an offset error injected in the attenuator stage, see Figures 2 and 4. The AD7864 contains an on-chip +2.5 V reference. To use this reference as the reference source for the AD7864, simply connect a 0.1 F disc ceramic capacitor from the VREF pin to AGND. The voltage that appears at this pin is internally buffered before being applied to the ADC. If this reference is used externally to the AD7864, it should be buffered, as the part has a FET switch in series with the reference output resulting in a source impedance for this output of 6 k nominal. The tolerance on the internal reference is 10 mV at 25C with a typical temperature coefficient of 25 ppm/C and a maximum error over temperature of 20 mV. If the application requires a reference with a tighter tolerance or the AD7864 needs to be used with a system reference, the user has the option of connecting an external reference to this VREF pin. The external reference will effectively overdrive the internal reference and thus provide the reference source for the ADC. The reference input is buffered before being applied to the ADC with the maximum input current of 100 A. Suitable reference sources for the AD7864 include the AD680, AD780, REF192 and REF43 precision +2.5 V references.
CIRCUIT DESCRIPTION Analog Input Section
The AD7864 is offered as three part types: the AD7864-1, where each input can be configured for 10 V or a 5 V input voltage range; the AD7864-3 which handles input voltage range 2.5 V; the AD7864-2, where each input can be configured to have a 0 V to +2.5 V or 0 V to +5 V input voltage range. -8- REV. A
AD7864
AD7864-1 AD7864-2
Figure 2 shows the analog input section of the AD7864-1. Each input can be configured for 5 V or 10 V operation on the AD7864-1. For 5 V (AD7864-1) operation, the VINXA and VINXB inputs are tied together and the input voltage is applied to both. For 10 V (AD7864-1) operation, the VINXB input is tied to AGND and the input voltage is applied to the VINXA input. The VINXA and VINXB inputs are symmetrical and fully interchangeable. Thus for ease of PCB layout on the 10 V range, the input voltage may be applied to the VINXB input while the VINXA input is tied to AGND.
Figure 3 shows the analog input section of the AD7864-2. Each input can be configured for 0 V to +5 V operation or 0 V to +2.5 V operation. For 0 V to +5 V operation, the VINXB input is tied to AGND and the input voltage is applied to the VINXA input. For 0 V to 2.5 V operation, the VINXA and VINXB inputs are tied together and the input voltage is applied to both. The VINXA and VINXB inputs are symmetrical and fully interchangeable. Thus for ease of PCB layout on the 0 V to +5 V range, the input voltage may be applied to the VINXB input while the VINXA input is tied to AGND. For the AD7864-2, R1 = 6 k and R2 = 6 k. Once again, the designed code transitions occur on successive integer LSB values. Output coding is straight (natural) binary with 1 LSB = FSR/4096 = 2.5 V/4096 = 0.61 mV, and 5 V/4096 = 1.22 mV, for the 0 V to 2.5 V and the 0 V to 5 V options respectively. Table II shows the ideal input and output transfer function for the AD7864-2.
AD7864-1
6k VREF TO ADC REFERENCE CIRCUITRY 2.5V REFERENCE
R1 VIN1A R2
AD7864-2
6k 2.5V REFERENCE
R3 VIN1B R4 T/H
TO INTERNAL COMPARATOR
VREF TO ADC REFERENCE CIRCUITRY VIN1A R1
AGND
Figure 2. AD7864-1 Analog Input Structure
For the AD7864-1, R1 = 6 k, R2 = 24 k, R3 = 24 k and R4 = 12 k. The resistor input stage is followed by the high input impedance stage of the track/hold amplifier. The designed code transitions take place midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs etc.) LSB size is given by the formula, 1 LSB = FSR/4096. For the 5 V range, 1 LSB = 10 V/4096 = 2.44 mV. For the 10 V range, 1 LSB = 20 V/4096 = 4.88 mV. Output coding is twos complement binary with 1 LSB = FSR/4096. The ideal input/ output transfer function for the AD7864-1 is shown in Table I.
Table I. Ideal Input/Output Code Table for the AD7864-1
R2 VIN1B T/H
TO INTERNAL COMPARATOR
Figure 3. AD7864-2 Analog Input Structure
Table II. Ideal Input/Output Code Table for the AD7864-2
Analog Input1 +FSR - 3/2 LSB +FSR - 5/2 LSB +FSR - 7/2 LSB
2
Digital Output Code Transition 111 . . . 110 to 111 . . . 111 111 . . . 101 to 111 . . . 110 111 . . . 100 to 111 . . . 101 000 . . . 010 to 000 . . . 011 000 . . . 001 to 000 . . . 010 000 . . . 000 to 000 . . . 001
Analog Inputl +FSR/2 - 3/2 LSB +FSR/2 - 5/2 LSB +FSR/2 - 7/2 LSB AGND + 3/2 LSB AGND + 1/2 LSB AGND - 1/2 LSB AGND - 3/2 LSB -FSR/2 + 5/2 LSB -FSR/2 + 3/2 LSB -FSR/2 + 1/2 LSB
2
Digital Output Code Transition 011 . . . 110 to 011 . . . 111 011 . . . 101 to 011 . . . 110 011 . . . 100 to 011 . . . 101 000 . . . 001 to 000 . . . 010 000 . . . 000 to 000 . . . 001 111 . . . 111 to 000 . . . 000 111 . . . 110 to 111 . . . 111 100 . . . 010 to 100 . . . 011 100 . . . 001 to 100 . . . 010 100 . . . 000 to 100 . . . 001
AGND + 5/2 LSB AGND + 3/2 LSB AGND + 1/2 LSB
NOTES 1 FSR is full-scale range and is 0 V to 2.5 V and 0 V to 5 V for AD7864-2 with VREF = +2.5 V. 2 1 LSB = FSR/4096 and is 0.61 mV (0 V to 2.5 V) and 1.22 mV (0 V to 5 V) for AD7864-2 with V REF = +2.5 V.
NOTES 1 FSR is full-scale range and is 20 V for the 10 V range and 10 V for the 5 V range, with V REF = +2.5 V. 2 1 LSB = FSR/4096 = 4.883 mV (10 V--AD7864-1) and 2.441 mV ( 5 V-- AD7864-1) with VREF = +2.5 V.
REV. A
-9-
AD7864
AD7864-3 SELECTING A CONVERSION SEQUENCE
Figure 4 shows the analog input section of the AD7864-3. The analog input range is 2.5 V on the VIN1A input. The VIN1B input can be left unconnected but if it is connected to a potential then that potential must be AGND.
AD7864-3
6k VREF TO ADC REFERENCE CIRCUITRY R1 VIN1A R2 T/H TO INTERNAL COMPARATOR 2.5V REFERENCE
Any subset of the four channels VIN1 to VIN4 can be selected for conversion. The selected channels are converted in an ascending order. For example if the channel selection includes VIN4, VIN1 and VIN3 then the conversion sequence will be VIN1, VIN3 and then VIN4. The conversion sequence selection my be made by using either the hardware channel select input pins (SL1 through SL4) or programming the channel select register. A logic high on a hardware channel select pin (or logic one in the channel select register) when CONVST goes logic high, marks the associated analog input channel for inclusion in the conversion sequence. Figure 5 shows the arrangement used. The H/S SEL controls a multiplexer which selects the source of the conversion sequence information, i.e., from the Hardware channel select pins (SL1 to SL4) or from the channel selection register. When a conversion is started the output from the multiplexer is latched until the end of the conversion sequence. The data bus Bits DB0 to DB3 (DB0 representing Channel 1 through DB3 representing Channel 4) are bidirectional and become inputs to the channel select register when RD is logic high and CS and WR are logic low. The logic state on DB0 to DB3 is latched into the channel select register when WR goes logic high.
H/S HARDWARE CHANNEL SELECT PINS SL1 SL2 SL3 SL4 CHANNEL SELECT REGISTER M U L T I P L E X E R SELECT INDIVIDUAL TRACK-AND-HOLDS FOR CONVERSION
VIN1B
Figure 4. AD7864-3 Analog Input Structure
For the AD7864-3, R1 = 6 k and R2 = 6 k. As a result, the VIN1A input should be driven from a low impedance source. The resistor input stage is followed by the high input impedance stage of the track/hold amplifier. The designed code transitions take place midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs, etc.) LSB size is given by the formula, 1 LSB = FSR/4096. Output coding is 2s complement binary with 1 LSB = FSR/ 4096 = 5 V/4096 = 1.22 mV. The ideal input/output transfer function for the AD7864-3 is shown in Table III.
Table III. Ideal Input/Output Code Table for the AD7864-3
DATA BUS D3 D2 D1 D0
LATCH
SEQUENCER
WR
Analog Inputl +FSR/2 - 3/2 LSB2 +FSR/2 - 5/2 LSB +FSR/2 - 7/2 LSB AGND + 3/2 LSB AGND + 1/2 LSB AGND - 1/2 LSB AGND - 3/2 LSB -FSR/2 + 5/2 LSB -FSR/2 + 3/2 LSB -FSR/2 + 1/2 LSB
Digital Output Code Transition 011 . . . 110 to 011 . . . 111 011 . . . 101 to 011 . . . 110 011 . . . 100 to 011 . . . 101 000 . . . 001 to 000 . . . 010 000 . . . 000 to 000 . . . 001 111 . . . 111 to 000 . . . 000 111 . . . 110 to 111 . . . 111 100 . . . 010 to 100 . . . 011 100 . . . 001 to 100 . . . 010 100 . . . 000 to 100 . . . 001
CS WR
TRANSPARENT WHILE WAITING FOR CONVST. LATCHED ON THE RISING EDGE OF CONVST AND DURING A CONVERSION SEQUENCE.
Figure 5. Channel Select Inputs and Registers
RD
t 13
WR
t 14
CS
t 15
NOTES 1 FSR is full-scale range is 5 V, with V REF = +2.5 V. 2 1 LSB = FSR/4096 = 1.22 mV (2.5 V - AD7864-3) with V REF = +2.5 V.
t 16
DATA
t 17
DATA IN
Figure 6. Channel Selection via Software Control
-10-
REV. A
AD7864
t1
CONVST BUSY
t ACQ t BUSY
QUIET TIME
t2 t CONV t8 t CONV t CONV t CONV
EOC
t 11
FRSTDATA
t 10
t 11
RD
t3
CS
t4
t5
t6
DATA 100ns H/S SEL 100ns SL1-SL4 VIN1 VIN2
t7
VIN3 VIN4
Figure 7. Timing Diagram for Reading During Conversion
TIMING AND CONTROL Reading Between Each Conversion in the Conversion Sequence
Figure 7 shows the timing and control sequence required to obtain the optimum throughput rate from the AD7864. To obtain the optimum throughput from the AD7864 the user must read the result of each conversion as it becomes available. The timing diagram in Figure 7 shows a read operation each time the EOC signal goes logic low. The timing in Figure 7 shows a conversion on all four analog channels (SL1 to SL4 = 1, see Channel Selection), hence there are four EOC pulses and four read operations to access the result of each of the four conversions. A conversion is initiated on the rising edge of CONVST. This places all four track/holds into hold simultaneously. New data from this conversion sequence is available for the first channel selected (VIN1) 1.65 s later. The conversion on each subsequent channel is completed at 1.65 s intervals. The end of each conversion is indicated by the falling edge of the EOC signal. The BUSY output signal indicates the end of conversion for all selected channels (four in this case). Data is read from the part via a 12-bit parallel data bus with standard CS and RD signals. The CS and RD inputs are internally gated to enable the conversion result onto the data bus. The data lines DB0 to DB11 leave their high impedance state when both CS and RD are logic low. Therefore, CS may be permanently tied logic low and the RD signal used to access the conversion result. Since each conversion result is latched into its output data register prior to EOC going logic low a further option would be to tie the EOC and RD pins together and use the rising edge of EOC to latch the conversion result. Although the AD7864 has some special features that permit reading during a conversion (e.g., a separate supply for the output data
drivers, VDRIVE), for optimum performance it is recommended that the read operation be completed when EOC is logic low, i.e., before the start of the next conversion. Although Figure 8 shows the read operation taking place during the EOC pulse, a read operation can take place at any time. Figure 8 shows a timing specification called "Quiet Time." This is the amount of time that should be left after a read operation and before the next conversion is initiated. The quiet time depends heavily on data bus capacitance but a figure of 50 ns to 100 ns is typical. The signal labeled FRSTDATA (First Data Word) indicates to the user that the pointer associated with the output data registers is pointing to the first conversion result by going logic high. The pointer is reset to point to the first data location (i.e., first conversion result,) at the end of the first conversion (FRSTDATA logic high). The pointer is incremented to point to the next register (next conversion result) when that conversion result is available. Hence, FRSTDATA in Figure 7 is seen to go low just prior to the second EOC pulse. Repeated read operations during a conversion will continue to access the data at the current pointer location until the pointer is incremented at the end of that conversion. Note FRSTDATA has an indeterminate logic state after initial power up. This means that for the first conversion sequence after power up, the FRSTDATA logic output may already be logic high before the end of the first conversion. This condition is indicated by the dashed line in Figure 7. Also the FRSTDATA logic output may already be high as a result of the previous read sequence as is the case after the fourth read in Figure 7. The fourth read (rising edge of RD) resets the pointer to the first data location. Therefore, FRSTDATA is already high when the next conversion sequence is initiated. See Accessing the Output Data Registers.
REV. A
-11-
AD7864
t1
CONVST BUSY
t BUSY t2
QUIET TIME
EOC
t8
RD
t3
CS
t4 t7
t6
DATA VIN1 VIN2
VIN3
VIN4
VIN1
t 10
FRSTDATA
t 10
Figure 8. Timing Diagram, Reading After the Conversion Sequence
Reading After the Conversion Sequence Using an External Clock
Figure 8 shows the same conversion sequence as Figure 7. In this case, however, the results of the four conversions (on VIN1 to VIN4) are read after all conversions have finished, i.e., when BUSY goes logic low. The FRSTDATA signal goes logic high at the end of the first conversion just prior to EOC going logic low. As mentioned previously FRSTDATA has an indeterminate state after initial power up, therefore FRSTDATA may already be logic high. Unlike the case when reading between each conversion the output data register pointer is incremented on the rising edge of RD because the next conversion result is available. This means FRSTDATA will go logic low after the first rising edge on RD. Successive read operations will access the remaining conversion results in an ascending channel order. Each read operation increments the output data register pointer. The read operation that accesses the last conversion result causes the output data register pointer to be reset so that the next read operation will access the first conversion result again. This is shown in Figure 8 with the fifth read after BUSY goes low accessing the result of the conversion on VIN1. Thus the output data registers act as a circular buffer in which the conversion results may be continually accessed. The FRSTDATA signal will go high when the first conversion result is available. Data is enabled onto the data bus DB0 to DB11 using CS and RD. Both CS and RD have the same functionality as described in the previous section. There are no restrictions or performance implications associated to the position of the read operations after BUSY goes low. The only restriction is that there is minimum time between read operations. Notice also that a "Quiet Time" is needed before the start of the next conversion.
The logic input INT/EXT CLK allows the user to operate the AD7864 using the internal clock oscillator or an external clock. The optimum performance is achieved by using the internal clock on the AD7864. The highest external clock frequency allowed is 5 MHz. This means a conversion time of 2.6 s compared to 1.65 s using the internal clock. In some instances, however, it may be useful to use an external clock when high throughput rates are not required. For example, two or more AD7864s may be synchronized by using the same external clock for all devices. In this way there is no latency between output logic signals like EOC due to differences in the frequency of the internal clock oscillators. Figure 9 shows how the various logic outputs are synchronized to the CLK signal. Each conversion requires 14 clocks. The output data register pointer is reset to point to the first register location on the falling edge of the 12 clock cycle of the first conversion in the conversion sequence-- See Accessing the Output Data Registers. At this point the logic output FRSTDATA goes logic high. The result of the first conversion is transferred to the output data registers on the falling edge of the 13 clock cycle. The FRSTDATA signal is reset on the falling edge of the 13 clock cycle of the next conversion, i.e., when the result of the second conversion is transferred to its output data register. As mentioned previously, the pointer is incremented by the rising edge of the RD signal if the result of the next conversion is available. The EOC signal goes logic low on the falling edge of the 13 clock cycle and is reset high again on the falling edge of the 14 clock cycle.
-12-
REV. A
AD7864
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 CLK 13 14
CONVST
FRSTDATA
EOC
RD
FIRST CONVERSION COMPLETE
LAST CONVERSION COMPLETE
BUSY
Figure 9. Using an External Clock
Standby Mode Operation
The AD7864 has a Standby Mode whereby the device can be placed in a low current consumption mode (5 A typ). The AD7864 is placed in standby by bringing the logic input STBY low. The AD7864 can be powered up again for normal operation by bringing STBY logic high. The output data buffers are still operational while the AD7864 is in standby. This means the user can still continue to access the conversion results while the AD7864 is in standby. This feature can be used to reduce the average power consumption in a system using low throughput rates. To reduce the average power consumption the AD7864 can be placed in standby at the end of each conversion sequence, i.e., when BUSY goes low and taken out of standby again prior the start of the next conversion sequence. The time it takes the AD7864 to come out of standby is called the "wake up" time. This wake-up time will limit the maximum throughput rate at which the AD7864 can be operated when powering down between conversion sequences. The AD7864 will wake-up in approximately 2 s when using an external reference. The "wake up" time is also 2 s when the standby time is less than 1 millisecond while using the internal reference. Figure 11 shows the wake-up time of the AD7864 for standby times greater than 1 millisecond. Note when the AD7864 is left in standby for periods of time greater than 1 millisecond the part will require more than 2 s to wake up. For example after initial power up, using the internal reference the AD7864 takes 6 ms to power up. The maximum throughput rate that can be achieved when powering down between conversions is 1/(tBUSY + 2 s) = 100 kSPS, approximately. When operating the AD7864 in a standby mode between conversions the power savings can be significant. For example with a throughput rate of 10 kSPS the AD7864 will be powered down (IDD = 5 A) for 90 s out of
100 s CONVST BUSY
every 100 s. See Figure 10. Therefore the average power consumption drops to (125/10) mW or 12.5 mW approximately.
1 0.9 POWER-UP TIME - ms 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.0001 0.001 0.01 0.1 STANDBY TIME - sec 1 -40 C +105 C +25 C
10
Figure 11. Power-Up Time vs. Standby Time Using the On-Chip Reference (Decoupled with 0.1 F Capacitor)
Accessing the Output Data Registers
There are four Output Data Registers, one for each of the four possible conversion results from a conversion sequence. The result of the first conversion in a conversion sequence is placed in Register 1 and the second result is placed in Register Number 2 and so on. For example if the conversion sequence VIN1, VIN3 and VIN4 is selected (see Conversion Sequence Selection) then the results of the conversion on VIN1, VIN3 and VIN4 are placed in Registers 1 to 3 respectively. The Output Data register pointer is reset to point to Register 1 at the end of the first conversion in the sequence, just prior to EOC going
t BUSY
7s
t BUSY tWAKEUP
STBY
IDD = 20 A
2s
Figure 10. Power-Down Between Conversion Sequences
REV. A
-13-
AD7864
low. At this point the logic output FRSTDATA will go logic high to indicate that the output data register pointer is addressing Register Number 1. When CS and RD are both logic low the contents of the addressed register are enabled onto the data bus (DB0-DB11). When reading the output data registers after a conversion sequence, i.e., when BUSY goes low, the register pointer is incremented on the rising edge of the RD signal as shown in Figure 12. However, when reading the conversion results during the conversion sequence the pointer will not be incremented until a valid conversion result is in the register to be addressed. In this case the pointer is incremented when the conversion has ended and the result has been transferred to the output data register. This happens just prior to EOC going low, therefore EOC may be used to enable the register contents onto the data bus as described in Reading During the Conversion Sequence. The pointer is reset to point to Register 1 on the rising edge of the RD signal when the last conversion result in the sequence is being read. In the example shown this means the pointer is set to Register 1 when the contents of Register 3 are read.
FRSTDATA OUTPUT DATA REGISTERS OE #1 DECODE 2-BIT COUNTER POINTER* OE #2 OE #3 OE #4 RESET RD CS *THE POINTER WILL NOT BE INCREMENTED BY A RISING EDGE ON RD UNTIL THE CONVERSION RESULT IS IN THE OUTPUT DATA REGISTER. THE POINTER IS RESET WHEN THE LAST CONVERSION RESULT IS READ (VIN1) (VIN3) (VIN4) NOT VALID O/P DRIVERS OE *ADDITIONAL PINS OMITTED FOR CLARITY VDRIVE R3 10k R5 10k
Positive Full-Scale Adjust
Apply a voltage of +9.9927 V (FS - 3/2 LSBs) at V1. Adjust R2 until the ADC output code flickers between 0111 1111 1110 and 0111 1111 1111.
Negative Full-Scale Adjust
Apply a voltage of -9.9976 V (-FS + 1/2 LSB) at V1 and adjust R2 until the ADC output code flickers between 1000 0000 0000 and 1000 0000 0001. An alternative scheme for adjusting full-scale error in systems which use an external reference is to adjust the voltage at the VREF pin until the full-scale error for any of the channels is adjusted out. The good full-scale matching of the channels will ensure small full-scale errors on the other channels.
INPUT RANGE = V1 R1 10k R2 500 R4 10k 10V
VINXA
AD7864*
AGND DB0 TO DB11
AD7864
Figure 13. Full-Scale Adjust Circuit
DYNAMIC SPECIFICATIONS
Figure 12. Output Data Registers
OFFSET AND FULL-SCALE ADJUSTMENT
In most Digital Signal Processing (DSP) applications, offset and full-scale errors have little or no effect on system performance. Offset error can always be eliminated in the analog domain by ac coupling. Full-scale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the ADC. Invariably, some applications will require that the input signal span the full analog input dynamic range. In such applications, offset and full-scale error will have to be adjusted to zero. Figure 13 shows a circuit which can be used to adjust the offset and full-scale errors on the AD7864 (VA1 on the AD7864-1 version is shown for example purposes only). Where adjustment is required, offset error must be adjusted before full-scale error. This is achieved by trimming the offset of the op amp driving the analog input of the AD7864 while the input voltage is a 1/2 LSB below analog ground. The trim procedure is as follows: apply a voltage of -2.44 mV (-1/2 LSB) at V1 in Figure 13 and adjust the op amp offset voltage until the ADC output code flickers between 1111 1111 1111 and 0000 0000 0000. Gain error can be adjusted at either the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). The trim procedures for both cases are as follows.
The AD7864 is specified and 100% tested for dynamic performance specifications as well as traditional dc specifications such as integral and differential nonlinearity. These ac specifications are required for the signal processing applications such as phased array sonar, adaptive filters and spectrum analysis. These applications require information on the ADC's effect on the spectral content of the input signal. Hence, the parameters for which the AD7864 is specified include SNR, harmonic distortion, intermodulation distortion and peak harmonics. These terms are discussed in more detail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal to noise ratio at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fS/2) excluding dc. SNR is dependent upon the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to noise ratio for a sine wave input is given by SNR = (6.02N + 1.76) dB where N is the number of bits. Thus for an ideal 12-bit converter, SNR = 74 dB. Figure 14 shows a histogram plot for 8192 conversions of a dc input using the AD7864 with 5 V supply. The analog input was set at the center of a code. It can be seen that all the codes appear in the one output bin indicating very good noise performance from the ADC. REV. A (1)
-14-
AD7864
9000 8000 7000 6000 5000 4000 3000 2000 1000 0 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 ADC CODE EFFECTIVE NUMBERS OF BITS 12 11 -40 C 10 +25 C 9 8 7 6 5 4
+105 C
0
500
1000 1500 2000 FREQUENCY - kHz
2500
3000
Figure 14. Histogram of 8192 Conversions of a DC Input
Figure 16. Effective Numbers of Bits vs. Frequency
Intermodulation Distortion
The output spectrum from the ADC is evaluated by applying a sine wave signal of very low distortion to the analog input. A Fast Fourier Transform (FFT) plot is generated from which the SNR data can be obtained. Figure 15 shows a typical 4096 point FFT plot of the AD7864 with an input signal of 99.9 kHz and a sampling frequency of 500 kHz. The SNR obtained from this graph is 72.6 dB. It should be noted that the harmonics are taken into account when calculating the SNR.
0 -10 -20 -30 -40 dB -50 -60 -70 -80 -90 -100 AD7864-1 @ +25 C 5V SUPPLY SAMPLING AT 499712Hz INPUT FREQUENCY OF 99857Hz 8192 SAMPLES TAKEN
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3 . . ., etc. Intermodulation terms are those for which neither m or n are equal to zero. For example, the second order terms include (fa + fb) and (fa - fb) while the third order terms include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb). Using the CCIF standard where two input frequencies near the top end of the input bandwidth are used, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. In this case, the input consists of two, equal amplitude, low distortion sine waves. Figure 17 shows a typical IMD plot for the AD7864.
0 -10 AD7864-1 @ +25 C 5V SUPPLY SAMPLING AT 131072Hz INPUT FREQUENCIES OF 48928Hz AND 50016Hz 4096 SAMPLES TAKEN
-110
0
50000
100000 150000 FREQUENCY - Hz
200000
250000
-20 -30 -40 dB
Figure 15. FFT Plot
Effective Number of Bits
The formula given in Equation 1 relates the SNR to the number of bits. Rewriting the formula, as in Equation 2, it is possible to get a measure of performance expressed in effective number of bits (N). SNR -1.76 N= (2) 6.02 The effective number of bits for a device can be calculated directly from its measured SNR. Figure 16 shows a typical plot of effective number of bits versus frequency for an AD7864-2.
-50 -60 -70 -80 -90
-100 0 10000 20000 30000 40000 FREQUENCY - Hz 50000 60000
Figure 17. IMD Plot
REV. A
-15-
AD7864
AC Linearity Plots Measuring Aperture Jitter
The plots shown in Figure 18 below show typical DNL and INL plots for the AD7864.
3.00E-01
A convenient way to measure aperture jitter is to use the relationship it is known to have with SNR (Signal to Noise plus distortion) given below: 1 SNRJITTER = 20 x log10 , where (2 x x f IN x ) SNR JITTER = Signal to Noise due to the rms time jitter = rms time jitter fIN = sinusoidal input frequency (1 MHz in this case) (3)
2.00E-01
1.00E-01 DNL - LSB
0.00E+00
-1.00E-01
-2.00E-01
From Equation 3 above it can be seen that the signal-to-noise ratio due to jitter degrades significantly with frequency. Therefore, at low input frequencies the measured SNR performance of the AD7864 is indicative of noise performance due to quantization noise and system noise only (72 dBs used as a typical figure here).
0 500 1000 1500 2000 2500 ADC CODE 3000 3500 4000
-3.00E-01
2.50E-01 2.00E-01 1.50E-01 1.00E-01 INL - LSB 5.00E-02 0.00E+00 -5.00E-02 -1.00E-01 -1.50E-01 -2.00E-01 -2.50E-01 0 500 1000 1500 2000 2500 ADC CODE 3000 3500 4000
Therefore, by measuring the overall SNR performance (including noise due to jitter, system and quantization) of the AD7864 a good estimation of the jitter performance of the AD7864 can be calculated.
12
11 10 9
ENOBs
8 7
6 5 900000
Figure 18. Typical DNL and INL Plots
950000 1000000 FREQUENCY - Hz 1050000 1100000
Figure 19. ENOBs of the AD7864 at 1 MHz
From Figure 19 above the ENOBs of the AD7864 at 1 MHz is approximately 11 bits. This is equivalent to 68 dBs SNR. SNRTOTAL = SNR JITTER + SNRQUANT = 68 dBs 68 dBs = SNR JITTER + 72 dBs (at 100 kHz) SNR JITTER = 70.2 dBs From (3) above 70.2 dBs = 20 x log10 [1/(2 x x 1 MHz x )] = 49 ps where is the rms jitter of the AD7864
-16-
REV. A
AD7864
MICROPROCESSOR INTERFACING
The high speed parallel interface of the AD7864 allows easy interfacing to most DSP processors and microprocessors. The ADC7864 interface of the AD7864 consists of the data lines (DB0-DB11), CS, RD, WR, EOC and BUSY.
AD7864-ADSP-2100/ADSP-2101/ADSP-2102 Interface
TMS320C5x
ADDRESS DECODE VIN1 VIN2 VIN3 VIN4 CS RD WR DB0-DB11 RD WE D0-D15 A0-A13 DS
Figure 20 shows an interface between the AD7864 and the ADSP-2100. The CONVST signal can be generated by the ADSP-2100 or from some other external source. Figure 20 shows the CS being generated by a combination of the DMS signal and the address bus of the ADSP-2100. In this way the AD7864 is mapped into the data memory space of the ADSP-2100. The AD7864 BUSY line provides an interrupt to the ADSP2100 when the conversion sequence is complete on all the selected channels. The conversion results can then be read from the AD7864 using successive read operations. Alternately, one can use the EOC pulse to interrupt the ADSP-2100 when the conversion on each channel is complete when reading between each conversion in the conversion sequence (Figure 7). The AD7864 is read using the following instruction MR0 = DM(ADC) where MR0 is the ADSP-2100 MR0 register and ADC is the AD7864 address.
ADSP-2100/1/2
ADDRESS DECODE VIN1 VIN2 VIN3 VIN4 CS RD WR DB0-DB11 RD WR D0-D24 A0-A13 DMS
AD7864
BUSY CONVST INTn PA0
Figure 21. AD7864-TMS320C5x Interface
AD7864-MC68000 Interface
An interface between the AD7864 and the MC68000 is shown in Figure 22. The conversion can be initiated from the MC68000 or from an external source. The AD7864 BUSY line can be used to interrupt the processor or, alternatively, software delays can ensure that conversion has been completed before a read to the AD7864 is attempted. Because of the nature of its interrupts, the 68000 requires additional logic (not shown in Figure 22) to allow it to be interrupted correctly. For further information on 68000 interrupts, consult the 68000 Users Manual. The MC68000 AS and R/W outputs are used to generate a separate RD input signal for the AD7864. RD is used to drive the 68000 DTACK input to allow the processor to execute a normal read operation to the AD7864. The conversion results are read using the following 68000 instruction: MOVE.W ADC,D0 where D0 is the 68000 D0 register and ADC is the AD7864 address.
MC68000
AD7864
BUSY CONVST IRQn DT1/F0 VIN1 VIN2 VIN3 VIN4 CS ADDRESS DECODE
A0-A15
Figure 20. AD7864-ADSP-2100 Interface
AD7864-TMS320C5x Interface
DTACK AS R/W
Figure 21 shows an interface between the AD7864 and the TMS320C5x. As with the previous interfaces, conversion can be initiated from the TMS320C5x or from an external source and the processor is interrupted when the conversion sequence is completed. The CS signal to the AD7864 is derived from the DS signal and a decode of the address bus. This maps the AD7864 into external data memory. The RD signal from the TMS320 is used to enable the ADC data onto the data bus. The AD7864 has a fast parallel bus so there are no wait state requirements. The following instruction is used to read the conversion results from the AD7864: IN D,ADC where D is Data Memory address and ADC is the AD7864 address.
RD
AD7864
DB0-DB11 D0-D15
CONVST
CLOCK
Figure 22. AD7864-MC68000 Interface
REV. A
-17-
AD7864
Vector Motor Control MULTIPLE AD7864s IN A SYSTEM
The current drawn by a motor can be split into two components: one produces torque and the other produces magnetic flux. For optimal performance of the motor, these two components should be controlled independently. In conventional methods of controlling a three-phase motor, the current (or voltage) supplied to the motor and the frequency of the drive are the basic control variables. However, both the torque and flux are functions of current (or voltage) and frequency. This coupling effect can reduce the performance of the motor because, for example, if the torque is increased by increasing the frequency, the flux tends to decrease. Vector control of an ac motor involves controlling phase in addition to drive and current frequency. Controlling the phase of the motor requires feedback information on the position of the rotor relative to the rotating magnetic field in the motor. Using this information, a vector controller mathematically transforms the three phase drive currents into separate torque and flux components. The AD7864, with its four-channel simultaneous sampling capability, is ideally suited for use in vector motor control applications. A block diagram of a vector motor control application using the AD7864 is shown in Figure 23. The position of the field is derived by determining the current in each phase of the motor. Only two phase currents need to be measured because the third can be calculated if two phases are known. VIN1 and VIN2 of the AD7864 are used to digitize this information. Simultaneous sampling is critical to maintain the relative phase information between the two channels. A current sensing isolation amplifier, transformer or Hall effect sensor is used between the motor and the AD7864. Rotor information is obtained by measuring the voltage from two of the inputs to the motor. VIN3 and VIN4 of the AD7864 are used to obtain this information. Once again the relative phase of the two channels is important. A DSP microprocessor is used to perform the mathematical transformations and control loop calculations on the information fed back by the AD7864.
DSP MICROPROCESSOR
Figure 24 shows a system where a number of AD7864s can be configured to handle multiple input channels. This type of configuration is common in applications such as sonar, radar, etc. The AD7864 is specified with maximum limits on aperture delay match. This means that the user knows the difference in the sampling instant between all channels. This allows the user to maintain relative phase information between the different channels. The AD7864 has a maximum aperture delay matching of 4 ns. All AD7864s use the same external SAR clock (5 MHz). Therefore, the conversion time for all devices will be the same and so all devices may be read simultaneously. The example shown in Figure 24 the data outputs of two AD7864s are enabled onto a 32-bit wide data bus when EOC goes low.
REF193
VIN1 EOC VIN2 VIN3 AD7864 VIN4 VREF CLKIN CS RD
ADSP-2106x
12 32
RD
VIN1 VIN2 VIN3 AD7864 VIN4 VREF CLKIN 5MHz CS RD
12
ADDRESS DECODE
Figure 24. Multiple AD7864s in Multichannel System
DAC TORQUE & FLUX CONTROL LOOP CALCULATIONS & TWO TO THREE PHASE INFORMATION TORQUE SETPOINT FLUX SETPOINT + + - TRANSFORMATION TO TORQUE & FLUX CURRENT COMPONENTS - VIN1 VIN2 DAC DAC DRIVE CIRCUITRY
IC IB IA VB 3 PHASE VA MOTOR
ISOLATION AMPLIFIERS
AD7864*
VIN3 VIN4 VOLTAGE ATTENUATORS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. Vector Motor Control Using the AD7864
-18-
REV. A
AD7864
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Plastic Quad Flatpack (S-44)
0.548 (13.925) 0.546 (13.875) 0.096 (2.44) MAX 0.037 (0.94) 0.025 (0.64) SEATING PLANE TOP VIEW
(PINS DOWN)
0.398 (10.11) 0.390 (9.91)
33 34 23 22
8 0.8
44
12 1 11
0.040 (1.02) 0.032 (0.81)
0.040 (1.02) 0.032 (0.81)
0.083 (2.11) 0.077 (1.96)
0.033 (0.84) 0.029 (0.74)
0.016 (0.41) 0.012 (0.30)
REV. A
-19-
PRINTED IN U.S.A.
C3226a-5-6/99

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